Analog and Mixed-Signal Test, 1998. ,
Production Testing of RF and System-on-a-Chip Devices for Wireless Communications, 2004. ,
Mixed-signal testing and DfT, Advances in Electronic Testing: Challenges and Methodologies, D. Gizopoulos, pp.301-336, 2006. ,
An Introduction to Mixed-Signal IC Test and Measurement ,
Production test challenges for highly integrated mobile phone SoCs, Proc. IEEE European Test Symposium, pp.17-22, 2010. ,
, IEEE Standard for Test Access Port and Boundary-Scan Architecture, pp.1-2013
, IEEE Standard for Mixed-Signal Test Bus, vol.1149, pp.4-2010
Oscillation-test strategy for analog and mixed-signal integrated circuits, Proc. IEEE VLSI Test Symposium, pp.476-482, 1996. ,
Oscillation-Based Test in Mixed-Signal Circuits, 2006. ,
End-to-end test strategy for wireless systems, Proc. IEEE International Test Conference, pp.940-946, 1995. ,
An architecture for self-test of a wire-less communication system, IEEE Communications Magazine, vol.37, issue.6, pp.98-102, 1999. ,
RF-BIST: loopback spectral signature analysis, Proc. Design, Automation, & Test in Europe Conference, pp.478-483, 2003. ,
Wafer-level RF test and DfT for VCO modulating transceiver architectures, Proc. IEEE VLSI Test Symposium, pp.217-222, 2004. ,
Embedded loopback test for RF ICs, IEEE Transactions on Instrumentation and Measurement, vol.54, issue.5, pp.1715-1720, 2005. ,
On-chip testing techniques for RF wireless transceivers, IEEE Design & Test of Computers, vol.23, issue.4, pp.268-277, 2006. ,
Built-in loopback test for IC RF transceivers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, issue.6, pp.933-946, 2010. ,
A built-in self-test strategy for wire-less communication systems, Proc. IEEE International Test Conference, pp.930-939, 1995. ,
Arbitrary-precision signal generation for mixed-signal built-inself-test, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.45, pp.1425-1457, 1998. ,
On-chip analog signal generation for mixed-signal built-in selftest, IEEE Journal of Solid-State Circuits, vol.34, issue.3, pp.318-348, 1999. ,
A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits, IEEE Journal of Solid-State Circuits, vol.37, issue.4, pp.499-514, 2002. ,
Techniques for high-frequency integrated test and measurement, IEEE Transactions on Instrumentation and Measurement, vol.52, issue.6, pp.1780-1786, 2003. ,
An on-chip spectrum analyzer for analog built-in testing, Journal of Electronic Testing: Theory and Applications, vol.21, issue.3, pp.205-219, 2005. ,
An integrated frequency response characterization system with a digital interface for analog testing, IEEE Journal of Solid-State Circuits, vol.41, issue.10, pp.2301-2313, 2006. ,
A broadband CMOS amplitude detector for on-chip RF measurements, IEEE Transactions on Instrumentation and Measurement, vol.57, issue.7, pp.1470-1477, 2008. ,
A built-in self-test technique for RF low-noise amplifiers, IEEE Transactions on Microwave Theory and Techniques, vol.56, issue.2, pp.1035-1042, 2008. ,
De-sign of a 0.9V 2.45 GHz self-testable and reliability-enhanced CMOS LNA, IEEE Journal of Solid-State Circuits, vol.43, issue.5, pp.1187-1194, 2008. ,
,
Structural approach for built-in tests in RF devices, Proc. IEEE International Test Conference, 2010. ,
Experiences with non-intrusive sensors for RF built-in test, Proc. IEEE International Test Conference, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00815233
Testable switched-capacitor filters, IEEE Journal of Solid-State Circuits, vol.28, issue.7, pp.719-724, 1993. ,
Concurrent error detection and fault-tolerance in lin-ear analog circuits using continuous checksums, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.1, issue.2, pp.138-150, 1993. ,
The design of analog self-checking cir-cuits, Proc. IEEE International Conference on VLSI Design, pp.67-70, 1994. ,
Analog check-ers with absolute and relative tolerances, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.14, issue.5, pp.607-612, 1995. ,
Test generation and concurrent error detection in current-mode A/D converters, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.14, issue.10, pp.1291-1298, 1995. ,
A methodology to perform online self-testing for fieldprogrammable analog array circuits, IEEE Transactions on Instrumentation and Measurement, vol.54, issue.5, pp.1751-1760, 2005. ,
Automatic design of optimal con-current fault detector for linear analog systems, Proc. IEEE Inter-national Symposium on Fault-Tolerant Computing, pp.184-191, 1999. ,
A current-mode testable de-sign of operational transconductance amplifier-capacitor filters, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.46, pp.401-413, 1999. ,
De-sign of self-checking fully differential circuits and boards, IEEE Trans-actions on Very Large Scale Integration (VLSI) Systems, vol.8, issue.2, pp.113-128, 2000. ,
Design of concurrent test hardware for linear analog circuits with constained hardware overhead, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, issue.7, pp.756-765, 2004. ,
Concurrent detection of erroneous responses in linear analog circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.5, pp.878-891, 2006. ,
An adaptive checker for the fully differential analog code, IEEE Journal of Solid-State Circuits, vol.41, issue.6, pp.1421-1429, 2006. ,
On-line error detection in wireless RF transmitters using real-time streaming data, Proc. IEEE International On-Line Testing Symposium, pp.159-164, 2006. ,
Self-calibration of input-match in RF front-end circuitry, IEEE Transactions on Circuits and Systems-II: Express Briefs, vol.52, issue.12, pp.821-825, 2005. ,
Enabling efficient built-in-self-calibration for RFICs, Proc. IEEE International Conference on Elec-tronics, Circuits and Systems, pp.492-495, 2011. ,
A new self-healing methodology for RF amplifier circuits based on os-cillation principles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, issue.10, pp.1835-1848, 2012. ,
,
Mixed-signal SoCs with in situ self-healing circuitry, IEEE Design & Test of Computers, vol.29, issue.6, pp.27-39, 2012. ,
Integrated self-healing for mm-wave power amplifiers, IEEE Transactions on Microwave Theory and Techniques, vol.61, issue.3, pp.352-363, 2013. ,
Fault diagnosis for linear systems via multifrequency measurements, IEEE Transactions on Circuits and Systems, vol.26, issue.7, pp.457-465, 1979. ,
Time-domain testing strategies and fault diagnosis for analog systems, IEEE Transactions on Instrumentation and Measurement, vol.39, issue.1, pp.157-162, 1990. ,
Analog circuit fault diagnosis based on sensitivity computation and functional testing, IEEE Design & Test of Computers, vol.9, issue.1, pp.30-39, 1992. ,
Analog fault diagnosis based on ramping power supply current signature clusters, IEEE Transactions on Circuits and Systems-II: Analog and Dig-ital Signal Processing, vol.43, pp.703-712, 1996. ,
Linear circuit fault diagnosis using neuromorphic analyzers, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.44, pp.188-196, 1997. ,
Fault diagnosis for mixed-signal electronic systems, Proc. IEEE Aerospace Conference, pp.169-179, 1999. ,
A new adaptive analog test and diagnosis system, IEEE Transactions on Instrumentation and Measurement, vol.49, issue.2, pp.223-227, 2000. ,
A modular fault-diagnosis system for analog electronic circuits using neural networks with wavelet transform as a preprocessor, IEEE Transactions on Instrumentation and Measurement, vol.56, issue.5, pp.1546-1554, 2007. ,
Diagnosis of assembly failures for system-in-package RF tuners, IEEE International Symposium on Circuits and Systems, pp.2286-2289, 2008. ,
Fault diagnosis of analog circuits based on machine learning, Proc. Design, Automation & Test in Europe Conference, pp.1761-1766, 2010. ,
URL : https://hal.archives-ouvertes.fr/hal-00558898
Block level bayesian diagnosis of analogue electronic circuits, Proc. Design, Automation & Test in Europe Conference, pp.1767-1772, 2010. ,
Test time reduction in Analogue/Mixed-signal de-vices by defect oriented testing: An industrial example, Proc. Design, Automation & Test in Europe Conference, 2011. ,
Diagnosis of local spot defects in analog circuits, IEEE Trans-actions on Instrumentation and Measurement, vol.61, issue.10, pp.2701-2712, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00743568
Prediction of analog performance parameters using fast transient testing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21, issue.3, pp.349-361, 2002. ,
Low-cost test of embedded RF/Analog/Mixed-signal circuits in SOPs, IEEE Transactions on Advanced Packaging, vol.27, issue.2, pp.352-363, 2004. ,
Signature testing of analog and RF circuits: Algorithms and methodology, IEEE Transactions on Circuits and Systems -I, vol.54, issue.5, pp.1018-1031, 2007. ,
,
Production deployment of a fast transient testing methodology for analog circuits: Case study and results, IEEE International Test Conference, pp.1174-1181, 2003. ,
A signature test framework for rapid production testing of RF circuits, Proc. Design, Automation and Test in Europe Conference, pp.186-191, 2002. ,
Concurrent RF test using optimized modulated RF stimuli, IEEE International Conference on VLSI Design, pp.1017-1022, 2004. ,
Low-cost alternate EVM test for wireless receiver systems, Proc. IEEE VLSI Test Symposium, pp.255-260, 2005. ,
Combining internal probing with artficial neural networks for optimal RFIC testing, Proc. IEEE International Test Conference, 2006. ,
A low-cost test methodology for dynamic specification testing of high-speed data converters, Journal of Electronic Testing: Theory and Applications, vol.23, issue.1, pp.95-106, 2006. ,
Dynamic specification testing and diagnosis of highprecision sigma-delta ADCs, IEEE Design & Test of Computers, vol.30, issue.4, pp.36-48, 2013. ,
Analog sensor based testing of phase-locked loop dynamic performance parameters, Proc. IEEE Asian Test Symposium, pp.50-55, 2013. ,
Alternate electrical tests for extracting mechanical parameters of MEMS accelerometer sensors, Proc. IEEE VLSI Test Symposium, pp.192-199, 2006. ,
Non-linear decision boundaries for testing analog circuits, IEEE Transactions on Computer-Aided De-sign of Integrated Circuits and Systems, vol.24, issue.11, pp.1760-1773, 2005. ,
Error moderation in low-cost machine-learning-based ,
URL : https://hal.archives-ouvertes.fr/hal-00348331
, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.2, pp.339-351, 2008.
Smart selection of indirect parameters for dc-based alternate RF IC testing, Proc. IEEE VLSI Test Symposium, pp.19-24, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00803453
Efficient selection of signatures for analog/rf alternate test, Proc. IEEE European Test Symposium, 2013. ,
, Genetic Algorithms in Search, Optimization, and Machine Learning, 1989.
Floating search methods in feature selection, Pattern Recognition Letters, vol.15, pp.1119-1125, 1994. ,
Alternate test of RF front ends with IP constraints: Frequency domain test generation and validation, Proc. IEEE International Test Conference, 2006. ,
Built-in test of RF components using mapped feature extraction sensors, IEEE VLSI Test Symposium, pp.243-248, 2005. ,
A DFT approach for testing embedded systems using DC sensors, IEEE Design & Test of Computers, vol.23, issue.6, pp.464-475, 2006. ,
A true power detector for RF PA built-in calibration and testing, Proc. Design, Automation, & Test in Europe Conference, pp.1-6, 2011. ,
RF front-end test using built-in sensors, IEEE Design & Test of Computers, vol.28, issue.6, pp.76-84, 2011. ,
URL : https://hal.archives-ouvertes.fr/hal-00672386
Built-in self-test of RF subsystems with integrated sensors, Journal of Electronic Testing: Theory and Applications, vol.28, issue.5, pp.557-569, 2012. ,
A current based self-test methodology for RF front-end circuits, Microelectronics Journal, vol.36, issue.12, pp.1091-1102, 2005. ,
Defect filter for alternate RF test, Proc. IEEE European Test Symposium, pp.101-106, 2009. ,
URL : https://hal.archives-ouvertes.fr/hal-00418402
Test generation for linear time-invariant analog circuits, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.46, pp.554-564, 1999. ,
Analog testing by characteristic observation inference, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, issue.9, pp.1353-1368, 1999. ,
Specification-driven test generation for analog circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.10, pp.1189-1201, 2000. ,
Classification of defective analog integrated circuits using artificial neural networks, Journal of Electronic Testing: Theory and Applications, vol.20, pp.25-37, 2004. ,
, Support Vector Machines and Other Kernel-Based Learning Methods, 2000.
Top-down induction of decision trees classifiers a survey, IEEE Transactions on Systems, Man, and Cybernetics-Part C: Applications and Reviews, vol.35, issue.46, pp.476-487, 2005. ,
Constructive neural-network learning algorithms for pattern classification, IEEE Transactions on Neural Networks, vol.11, issue.2, pp.436-451, 2000. ,
A constructive algorithm that converges for real-valued input patterns, International Journal of Neural Systems, vol.5, issue.1, pp.59-66, 1994. ,
Analog neural network design for RF built-in self-test, Proc. IEEE International Test Conference, 2010. ,
URL : https://hal.archives-ouvertes.fr/hal-00560465
Adaptive alternate analog test, IEEE Design & Test of Computers, vol.29, issue.4, pp.71-79, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00625043
Making predictive analog/RF alternate test strategy independent of training set size, Proc. IEEE International Test Conference, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00803564
A comprehensive approach for modeling and testing analog and mixed-signal devices, Proc. IEEE International Test Conference, pp.169-176, 1990. ,
Developing linear error models for analog devices, IEEE Transactions on Instrumentation and Mea-surement, vol.43, issue.2, pp.157-163, 1994. ,
Test-point selection and testability measures via QR factorization of linear models, IEEE Transactions on Instrumentation and Measurement, vol.36, issue.2, pp.406-410, 1987. ,
Iterative test-point selection for analog circuits, Proc. IEEE VLSI Test Symposium, pp.66-71, 1996. ,
A rigorous exposition of the LEMMA method for analog and mixed-signal testing, IEEE Transactions on Instrumentation and Measurement, vol.48, issue.5, pp.978-985, 1999. ,
Minimizing production test time to detect faults in analog circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.13, issue.6, pp.796-813, 1994. ,
Test set selection for structural faults in analog IC's, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, issue.7, pp.1026-1039, 1999. ,
Optimal ordering of analog integrated circuit tests to minimize test time, ACM/IEEE Design Automation Conference, pp.494-499, 1991. ,
Predictive subset testing: Optimizing IC parametric performance testing for quality, cost, and yield, IEEE Transactions on Semiconductor Manufacturing, vol.2, issue.3, pp.104-113, 1989. ,
Specification test compaction for analog circuits and MEMS, Proc. Design, Automation & Test in Europe Conference, pp.164-169, 2005. ,
URL : https://hal.archives-ouvertes.fr/hal-00181510
Statistical test compaction using binary decision trees, IEEE Design & Test of Computers, vol.23, issue.6, pp.452-462, 2006. ,
RF specification test compaction using learning machines, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, pp.998-1002, 2010. ,
URL : https://hal.archives-ouvertes.fr/hal-00493365
Statistical methods for the estimation of process variation effects on circuit operation, IEEE Transactions on Electronics Packaging Manufacturing, vol.28, issue.4, pp.364-375, 2005. ,
Template-free symbolic performance modeling of analog circuits via canonical-form functions and genetic programming, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol.28, issue.8, pp.1162-1175, 2009. ,
Fast and accurate DPPM computation using model based filtering, Proc. IEEE European Test Symposium, pp.165-170, 2011. ,
Estimation of test metrics for the optimisation of analogue circuit testing, Journal of Electronic Testing: Theory and Applications, vol.23, issue.6, pp.471-484, 2007. ,
URL : https://hal.archives-ouvertes.fr/hal-00522014
Evaluation of analog/RF test measurements at the design stage, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.4, pp.582-590, 2009. ,
URL : https://hal.archives-ouvertes.fr/hal-00379139
A generic data-driven nonparametric framework for variability analysis of integrated circuits in nanometer technologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.7, pp.1038-1046, 2009. ,
Estimation of analog parametric test metrics using copulas, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, issue.9, pp.1400-1410, 2011. ,
URL : https://hal.archives-ouvertes.fr/hal-00648885
Test development through defect and test escape level estimation for data converters, Journal of Electronic Testing: Theory and Applications, vol.22, issue.4-6, pp.313-324, 2006. ,
Test metrics model for analog test development, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, issue.7, pp.1116-1128, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00743570
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade, ACM/IEEE Design Automation Conference, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00975424
Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.8, pp.1176-1189, 2009. ,
An Introduction to Statistical Modeling of Extreme Values, ser. Springer Series in Statistics, 2001. ,
Hierarchical yield estimation of large analog integrated circuits, IEEE Journal of Solid-State Circuits, vol.28, issue.3, pp.203-209, 1993. ,
Hierarchical parametric test metrics estimation: A ?? converter BIST case study, Proc. IEEE International Conference on Computer Design, pp.78-83, 2009. ,
URL : https://hal.archives-ouvertes.fr/hal-00471554
Detection of catastrophic faults in ana-log integrated circuits, IEEE Transactions on Computer-Aided Design, vol.8, issue.2, pp.114-130, 1989. ,
Test vector generation for linear analog devices, Proc. IEEE International Test Conference, pp.592-599, 1991. ,
Multifrequency analysis of faults in analog circuits, IEEE Design & Test of Computers, vol.12, issue.2, pp.70-80, 1995. ,
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets, Journal of Electronic Testing: Theory and Applications, vol.9, issue.1-2, pp.43-57, 1996. ,
URL : https://hal.archives-ouvertes.fr/hal-00013266
Probabilistic fault detection and the selection of measurements for analog integrated circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, issue.9, pp.862-872, 1998. ,
Automatic analog test signal generation using multifrequency analysis, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.46, pp.565-576, 1999. ,
Closing the gap between analog and digital testing, IEEE Transactions on Computer-Aided De-sign of Integrated Circuits and Systems, vol.20, issue.2, pp.307-314, 2001. ,
Dynamic supply current testing of analog cir-cuits using wavelet transform, Proc. IEEE VLSI Test Symposium, pp.302-307, 2002. ,
Decreasing test qualification time in AMS and RF systems, IEEE Design & Test of Computers, vol.25, issue.1, pp.29-37, 2008. ,
Fault modeling for the testing of mixed integrated circuits, Proc. IEEE International Test Conference, pp.564-572, 1991. ,
An experimental approach to analog fault models, Proc. IEEE Custom Integrated Circuits Conference, 1991. ,
Industrial relevance of analog IFA: A fact or a fiction, Proc. IEEE International Test Conference, pp.61-70, 1995. ,
Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits, Proc. IEEE European Design & Test Conference, pp.464-468, 1995. ,
Generation of optimised fault lists for simulation of analogue circuits and test programs, IEE Proceedings, vol.146, issue.6, pp.355-360, 1999. ,
Defect-oriented testing of RF circuits, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol.27, issue.5, pp.920-931, 2008. ,
Fault analysis and simulation of large scale industrial mixed-signal circuits, Proc. Design, Automation & Test in Europe Conference, pp.565-570, 2013. ,
Challenges in analog and mixed-signal fault models, IEEE Circuits & Devices Magazine, vol.12, issue.1, pp.16-19, 1996. ,
Hierarchical fault modeling for analog and mixed-signal circuits, Proc. IEEE VLSI Test Symposium, pp.96-101, 1992. ,
Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis, Proc. IEEE International Test Conference, 1997. ,
Test metrics for analog parametric faults, Proc. IEEE VLSI Test Symposium, pp.226-234, 1999. ,
Parametric fault simula-tion and test vector generation, Proc. Design, Automation & Test in Europe Conference, pp.650-656, 2000. ,
Test limitations of parametric faults in analog test, IEEE Transactions on Instrumentation and Measurement, vol.52, issue.5, pp.1444-1454, 2003. ,
A static linear behavior analog fault model for switched-capacitor circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, issue.4, pp.597-609, 2012. ,
Scalable and efficient analog parametric fault identification, Proc. IEEE/ACM International Conference on Computer-Aided Design, pp.387-392, 2013. ,
Efficient monte carlo-based analog parametric fault modelling, Proc. IEEE VLSI Test Symposium, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01060258
Analog test metrics estimates with PPM accuracy, Proc. IEEE/ACM International Conference on Computer-Aided Design, pp.241-247, 2010. ,
URL : https://hal.archives-ouvertes.fr/hal-00556698
Testing analog and mixed-signal integrated circuits using oscillation-test method, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, issue.7, pp.745-753, 1997. ,
Design for testability of embedded integrated operational amplifiers, IEEE Journal of Solid-State Circuits, vol.33, issue.4, pp.573-81, 1998. ,
Oscillation-test methodology for low-cost testing of active analog filters, IEEE Transactions on Instrumentation and Measurement ,
Design of oscillation-based test structures for active RC filters, IEE Proceedings-Circuits, Devices, and Systems, vol.147, pp.297-302, 2000. ,
Practical oscillationbased test of integrated filters, IEEE Design & Test of Computers, vol.19, issue.6, pp.64-72, 2002. ,
A comprehensive signature analysis scheme for oscillation-test, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22, issue.10, pp.1409-1423, 2003. ,
Application of predictive oscillation-based test to a CMOS opAmp, IEEE Transactions on Instrumentation and Measurement, vol.59, issue.8, pp.2076-2082, 2010. ,
Complex oscillation-based test and its application to analog filters, IEEE Transactions on Circuits and systems I: Regular Papers, vol.57, issue.5, pp.956-969, 2010. ,
Efficient and accurate testing of analog-to-digital converters using oscillation-test method, Proc. European Design and Test Conference, pp.348-352, 1997. ,
Oscillation built-in self-test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits, Proc. IEEE International Test Conference, pp.786-795, 1997. ,
Oscillation-based test in oversampling ?? modulators, Microelectronics Journal, vol.33, pp.799-806, 2002. ,
Low-cost specification based testing of RF amplifier circuits using oscillation principles, Journal of Electronic Testing: Theory and Applications, vol.26, issue.1, pp.13-24, 2010. ,
Evaluation of the oscillation-based test methodology for micro-electro-mechanical systems, Proc. IEEE VLSI Test Symposium, pp.439-444, 2002. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00268484
Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology, Proc. IEEE VLSI Test Symposium, pp.166-171, 1997. ,
A high quality analog oscillator using oversampling D/A converters technique, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.41, pp.437-444, 1994. ,
Non-linear shaping SC oscillator with enhanced linearity, IEEE Journal of Solid-State Circuits, vol.42, issue.11, pp.2421-2431, 2007. ,
A low thd, low power, high output-swing time-mode-based tunable oscillator via digital harmonic-cancellation technique, IEEE Journal of Solid-State Circuits, vol.45, issue.5, pp.1061-1071, 2010. ,
Analog sinewave signal generators for mixed-signal built-in test applications, Journal of Electronic Testing: Theory and Applications, vol.27, issue.3, pp.305-320, 2011. ,
Sinusoidal signal generation for mixedsignal BIST using a harmonic-cancellation technique, Proc. IEEE Latin American Symposium on Circuits and Systems, pp.1-4, 2013. ,
Low-distortion sine wave generation using a novel harmonic cancellation technique, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.60, issue.5, pp.1122-1134, 2013. ,
A high-quality analog oscillator using oversampling DA conversion techniques, Proc. IEEE International Symposium on Circuits and Systems, pp.1298-1301, 1993. ,
A cost effective BIST second-order ?? modulator, Proc. of IEEE Workshop on Design and Di-agnostics of Electronic Circuits and Systems, pp.1-6, 2008. ,
An implementation of memory-based on-chip analogue test signal generation, Proc. IEEE Asia and South Pacific Design Automation Conference, pp.663-668, 2003. ,
URL : https://hal.archives-ouvertes.fr/hal-00012867
Controlled sine wave fitting for ADC test, Proc. IEEE International Test Conference, pp.963-971, 2004. ,
Accurate digital synthesis of sinewaves, IEEE Transactions on Instrumentation and Measurement, vol.57, issue.3, pp.522-529, 2008. ,
A new sigma-delta modulator architecture for testing using digital stimulus, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, issue.1, pp.206-213, 2004. ,
A stereo ?? ADC architecture with embedded SNDR self-test, Proc. IEEE International Test Conference, 2007. ,
URL : https://hal.archives-ouvertes.fr/hal-00222053
A decorrelating design-for-digital-testability scheme for ?? modulators, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, issue.1, pp.60-73, 2009. ,
Ternary stimulus for fully digital dynamic testing of SC ?? ADCs, IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00745378
High accuracy stimulus generation for A/D converter BIST, Proc. IEEE International Test Conference, pp.1031-1039, 2002. ,
Testing second-order delta-sigma modulators using pseudo-random patterns, Microelectronics Journal, vol.33, issue.10, pp.807-814, 2002. ,
Ac-curate and efficient on-chip spectral analysis for built-in testing and calibration approaches, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, issue.3, pp.49-506, 2014. ,
, IEEE Standard for Digitizing Waveform Recorders, IEEE Std, pp.1057-2007
Controlled sine wave fitting for ADC test, Proc. IEEE International Test Conference, pp.963-971, 2004. ,
A fully integrated built-in self-test ?? ADC based on the modified controlled sine-wave fitting procedure, IEEE Transactions on Instrumentation and Measurement, vol.59, issue.9, pp.2334-2344, 1996. ,
Optimal high-resolution spectral analyzer, Proc. Design, Automation and Test in Europe Conference, pp.62-67, 2008. ,
A BIST architecture for sigma delta ADC testing based on embedded NOEB self-test and CORDIC algorithm, Proc. International Conference on Design and Technology of Interated Systems in Nanoscale Era, pp.1-7, 2004. ,
A low-cost adaptive ramp generator for analog BIST applications, Proc. IEEE VLSI Test Symposium, pp.266-271, 2001. ,
On-chip ramp generators for mixed-signal BIST and ADC self-test, IEEE Journal of Solid-State Circuits, vol.38, issue.2, pp.263-273, 2003. ,
A self calibrated ADC BIST methodology, Proc. IEEE VLSI Test Symposium, pp.117-122, 2002. ,
DNL ADC testing by the exponential shaped voltage, IEEE Transactions on Instrumentation and Measurement, vol.52, issue.3, pp.946-949, 2003. ,
Ac-curate testing of analog-todigital converters using low linearity signals with stimulus error identification and removal, IEEE Transactions on Instrumentation and Measurement, vol.54, issue.3, p.11881199, 2005. ,
Enhanced double-histogram test, Electronics Letters, vol.45, issue.7, pp.349-351, 2009. ,
Optimizing sinusoidal histogram test for low cost ADC BIST, Journal of Electronic Testing: Theory and Applications, vol.17, issue.3-4, pp.255-266, 2001. ,
Optimal schemes for ADC BIST based on histogram, Proc. IEEE Asian Test Symposium, pp.52-57, 2005. ,
Linearity testing of A/D converters using selective code measurement, Journal of Electronic Testing: Theory and Applications, vol.24, issue.6, pp.567-576, 2008. ,
High-resolution ADC linearity testing using a fully digital-compatible BIST strategy, IEEE Transactions on Instrumentation and Measurement, vol.58, issue.8, pp.2697-2705, 2009. ,
Transition-code based linearity test method for pipelined ADCs with digital error correction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.19, issue.12, pp.2158-2169, 2010. ,
Reduced-code linearity testing of pipeline ADCs, IEEE Design & Test, vol.30, issue.6, pp.80-88, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-01137870
Low-cost digital detection of paremetric faults in cascaded sigmadelta modulators, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, issue.7, pp.1326-1338, 2009. ,
Sigma-delta testability for pipeline A/D converters, Proc. Design, Automation and Test in Europe Conference, 2014. ,
BIST method for die-level process parameter variation monitoring in analog/mixed-signal in-tegrated circuits, Proc. Design, Automation & Test in Europe Conference, pp.1301-1306, 2007. ,
A 1-MHz area-efficient on-chip spectrum analyzer for analog testing, Journal of Electronic Testing: Theory and Applications, vol.22, issue.4, 2006. ,
FPGA-based analog functional measurements for adaptive control in mixed-signal systems, IEEE Transactions on Industrial Electronics, vol.54, issue.4, pp.1885-1897, 2010. ,
A BIST solution for frequency domain characterization of analog circuits, Journal of Electronic Testing: Theory and Applications, vol.26, issue.4, pp.429-441, 2010. ,
Bist for d/a and a/d converters, IEEE Design & Test of Computers, vol.13, issue.4, pp.40-49, 1996. ,
analogue network of converters": A DFT technique to test a complete set of ADCs and DACs embedded in a complex SiP or SoC, Proc. IEEE European Test Symposium, pp.211-216, 2007. ,
URL : https://hal.archives-ouvertes.fr/tel-00364546
BIST for phase-locked loops in digital applications, Proc. IEEE International Test Conference, pp.532-540, 1999. ,
A high resolution CMOS time-to-digital converter utilizing a Vernier delay line, IEEE Journal of Solid-State Circuits, vol.35, issue.2, pp.240-247, 2000. ,
A synthesizable, fast and high-resolution timing measurement device using a component-invariant Vernier delay line, Proc. IEEE International Test Conference, pp.858-867, 2001. ,
Embedded timing analysis: a SoC infrastructure, IEEE Design & Test of Computers, vol.19, issue.3, pp.22-34, 2002. ,
On-chip digital jitter measurement, from mega-hertz to gigahertz, IEEE Design & Test of Computers, vol.21, issue.4, pp.314-321, 2004. ,
A low-cost jitter measurement technique for bist applications, Journal of Electronic Testing: Theory and Applications, vol.22, issue.3, pp.219-228, 2006. ,
On-chip measurement of the jitter transfer function of chargepump phase-locked loops, IEEE Journal of Solid-State Circuits, vol.33, issue.3, pp.483-491, 1998. ,
On-chip measurement of jitter transfer and supply sensitivity of PLL/DLLs, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.56, issue.6, pp.449-453, 2009. ,
PFD output monitoring for RF PLL BIST, Proc. IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, 2008. ,
URL : https://hal.archives-ouvertes.fr/hal-00346513
A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection, Proc. IEEE VLSI Test Symposium, 2013. ,
An all-digital built-in self-test for high-speed phase-locked loops, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.48, pp.141-150, 2001. ,
On-chip digital jitter measurement, from megahertz to gigahertz, IEEE Design & Test of Computers, vol.20, issue.1, pp.60-67, 2003. ,
Detailed characterization of transceiver parameters through loopback-based BiST, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, issue.6, pp.901-911, 2010. ,
Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters, Proc. IEEE VLSI Test Symposium, 2013. ,
Zero-overhead self test and calibration of RF transceivers, Proc. IEEE International Test Conference, 2013. ,
Built-in self-test and characterization of polar transmitter parameters in the loop-back mode, Proc. Design, Automation, & Test in Europe Conference, 2014. ,
A system-level alternate test approach for specification test of RF transceivers in loopback mode, Proc. IEEE International Conference on VLSI Design, pp.289-294, 2005. ,
Alternate loop-back di-agnostic tests for waferlevel diagnosis of modern wireless transceivers using spectral signatures, Proc. IEEE VLSI Test Symposium, pp.222-227, 2006. ,
Thermal coupling in integrated circuits: application to thermal testing, IEEE Journal of Solid-State Circuits, vol.36, issue.1, pp.81-91, 2001. ,
URL : https://hal.archives-ouvertes.fr/hal-01550679
Structural RFIC device testing through built-in thermal monitoring, IEEE Communications Magazine, vol.41, issue.9, pp.98-104, 2003. ,
Electrothermal design procedure to observe rf circuit power and linearity characteristics with a homodyne differential temperature sensor, IEEE Transactions on, issue.99, pp.1-1, 2011. ,
DC temperature measurements for power gain monitoring in RF power amplifiers, Proc. IEEE International Test Conference, 2012. ,
Defect-oriented non-intrusive RF test using on-chip temperature sensors, Proc. IEEE VLSI Test Symposium, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00975942