Ternary Stimulus for Fully Digital Dynamic Testing of SC ΣΔ ADCs

Mat. Dubois (1) , Haralampos-G Stratigopoulos (1) , Salvador Mir (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

In this paper, a ternary stimulus is proposed for testing $Sigma Delta$ SD Analog-to-Digital Converters (ADCs). The ternary stimulus is composed of three logic levels {-1,0,1} and is obtained by adding a binary stream with a delayed version of itself. Only four switches are added to the input stage of the modulator of the $Sigma Delta$ ADC for facilitating the injection of the ternary stimulus. Compared to a binary stimulus, the ternary stimulus contains less quantization noise and allows measuring the SNDR of the $Sigma Delta$ ADC for the whole input dynamic range. We discuss the optimization of the ternary stimulus and we demonstrate its efficiency using behavioral simulations of a second-order switched-capacitor (SC) $Sigma Delta$ modulator.

Mots clés: accuracy-issues; optimization; delay

Domaines: Micro et nanotechnologies/Microélectronique

Mat. Dubois, Haralampos-G Stratigopoulos, Salvador Mir. Ternary Stimulus for Fully Digital Dynamic Testing of SC ΣΔ ADCs. IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMSTW'12), May 2012, Taipei, Taiwan. pp.5-10, ⟨10.1109/IMS3TW.2012.12⟩. ⟨hal-00745378⟩