Analog neural network design for RF built-in self-test

D. Maliuk (1) , Haralampos-G Stratigopoulos (2) , K. Huang (2, 3) , Y. Makris (1)

1 Department of Electrical Engineering [Yale University]
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
3 Institute of VLSI Design

A stand-alone built-in self-test architecture mainly consists of three components: a stimulus generator, measurement acquisition sensors, and a measurement processing mechanism to draw out a straightforward Go/No-Go test decision. In this paper, we discuss the design of a neural network circuit to perform the measurement processing step. In essence, the neural network implements a non-linear classifier which can be trained to map directly sensor-based measurements to the Go/No-Go test decision. The neural network is fabricated as a single chip and is put to the test to recognize faulty from functional RF LNA instances. Its decision is based on the readings of two amplitude detectors that are connected to the input and output ports of the RF LNA. We discuss the learning strategy and the generation of information-rich training sets. It is shown that the hardware neural network has comparable learning capabilities with its software counterpart.

Mots clés: built-in self test; RF applications

Domaines: Micro et nanotechnologies/Microélectronique

D. Maliuk, Haralampos-G Stratigopoulos, K. Huang, Y. Makris. Analog neural network design for RF built-in self-test. IEEE International Test Conference (ITC'10), Oct 2010, Austin, TX, United States. pp.23.2, ⟨10.1109/TEST.2010.5699272⟩. ⟨hal-00560465⟩