Quantitative evaluation of reliability and performance for STT-MRAM

Liuyang Zhang (1, 2) , Aida Todri-Sanial (2) , Wang Kang (1) , Youguang Zhang (1) , Lionel Torres (3) , Yuanqing Cheng (1) , Weisheng Zhao (1)

1 BUAA - Beihang University
2 SmartIES - Smart Integrated Electronic Systems
3 ADAC - ADAptive Computing

Due to its non-volatility, high access speed, ultra low power consumption and unlimited writing/reading cycles, STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has emerged as the most promising candidate for the next generation universal memory. However, the process of commercialization of STT-MRAM is hampered by its poor reliability. Generally, these reliability issues are caused by the PVT (Process Variations, Voltage, and Temperature) of both MTJ (Magnetic Tunneling Junction) and transistor. Mitigation and alleviating the impacts of the intrinsic properties and PVT on STT-MRAM is a challenging work. This paper discusses the errors occurring in STT-MRAM resulting from its poor reliability, and analyzes the causes of such errors. To obtain a quantitative assessment of PVT impact on STT-MRAM reliability, we investigate three aspects: writing/reading operation error rate, power consumption and access delay of a single cell. This study is carried out on Cadence platform for 45 nm technology node and the PMA (Perpendicular Magnetic Anisotropy) MTJ model used in the investigation comes from SP INLIB. These quantitative information would be helpful for designing reliability enhancing strategies of STT-MRAM.

Mots clés: Transistors; Magnetic tunneling; Error analysis; Power demand; Tunneling magnetoresistance; Writing; Reliability

Domaines: Micro et nanotechnologies/Microélectronique

Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, et al.. Quantitative evaluation of reliability and performance for STT-MRAM. ISCAS: International Symposium on Circuits and Systems, May 2016, Montréal, QC, Canada. pp.1150-1153, ⟨10.1109/ISCAS.2016.7527449⟩. ⟨lirmm-01446275⟩