An Innovative Timing Slack Monitor for Variation Tolerant Circuits

Bettina Rebaud (1) , Marc Belleville (1) , Edith Beigné (1) , Michel Robert (2) , Philippe Maurine (2) , Nadine Azemard (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 SysMIC - Conception et Test de Systèmes MICroélectroniques

To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure, coupled with a specific detection window generation, embedded within the clock-tree, can anticipate timing violations to prevent system failures in real-time. Performances simulated in a 45 nm technology demonstrate a scalable, low power and low area cell which can be easily inserted in a standard CAD flow.

Keywords: Clock Tree; Variability; Monitor; Timing slack; Performance; Reliability; Adaptation

Domains: Micro and nanotechnologies/Microelectronics

Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. An Innovative Timing Slack Monitor for Variation Tolerant Circuits. ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩. ⟨lirmm-00371174⟩