Temperature Dependency in UDSM Process

Benoit Lasbouygues (1) , Robin M. Wilson (2) , Philippe Maurine (1) , Nadine Azemard (1) , Daniel Auvergne (1)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 ST-CROLLES - STMicroelectronics [Crolles]

In low power UDSM process the use of reduced supply voltage with high threshold voltages may reverse the temperature dependence of designs. In this paper we propose a model to define the true worst Process, Voltage and Temperature conditions to be used to verify a design. This model will provide an accurate worst case definition for high performance designs where standard design margins are not applicable. This model is validated at either cell level or path level on two different 130nm process.

Domaines: Micro et nanotechnologies/Microélectronique

Benoit Lasbouygues, Robin M. Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependency in UDSM Process. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩. ⟨lirmm-00106077⟩