Gate stress reliability of a novel trench-based Triple Gate Transistor

R. Gay (1, 2) , V. Della Marca (2) , Hassen Aziza (2, 3) , P. Laine (4) , A. Regnier (1) , S. Niel (1) , A. Marzaki (1)

1 ST-ROUSSET - STMicroelectronics [Rousset]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 AMU - Aix Marseille Université
4 EVA - Ecophysiologie Végétale, Agronomie et Nutritions NCS

This paper addresses the reliability on a novel trench-based Triple Gate Transistor (TGT) fabricated in a 40nm embedded Non-Volatile Memory (e-NVM) technology. In the studied device, two vertical transistors are integrated in deep trenches alongside the main planar transistor to build a TGT. The reliability of this device is investigated targeting the gate oxide degradation, that represents one of the major reliability issues in e-NVM environment. Gate stress tests are motivated by the possibility to use independently trench transistors and the main planar transistor. Thus, the reliability of each gate oxide needs to be studied separately to the others. Moreover, different DC and AC stress tests are performed and analysed to understand the degradation mechanisms effecting the TGT device.

Domains: Micro and nanotechnologies/Microelectronics

R. Gay, V. Della Marca, Hassen Aziza, P. Laine, A. Regnier, et al.. Gate stress reliability of a novel trench-based Triple Gate Transistor. Microelectronics Reliability, 2021, 126, pp.114233. ⟨10.1016/j.microrel.2021.114233⟩. ⟨hal-03500202⟩