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Coarse/fine delay element design in 28 nm FD-SOI

Abstract : This chapter starts by highlighting the requirements and existing techniques in producing digital delay, summarizing the state of the art. Subsequently, a topology assessment is presented based on specified performance metrics. The proposed delay cell which was designed, fabricated, and characterized is then described. Specifically, the proposed design is based on a topology with low-supply-noise sensitivity and low jitter. Functionality is extended to support coarse/fine control for the output delay value, without the need for additional hardware. This is made possible by taking advantage of the body-biasing capabilities available in FD-SOI technology. The proposed delay element presents unique performance characteristics in terms of the achieved delay resolution and delay dynamic range. The chapter concludes with the demonstration of a delay line prototype, fabricated in ST 28 nm FD-SOI technology. After a general overview of delay techniques the proposed topology is described, by focusing on the major design aspects. Measurement results are then presented and a short discussion follows on the characterization findings.
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Contributor : Antoine Frappé Connect in order to contact the contributor
Submitted on : Wednesday, October 13, 2021 - 10:07:45 PM
Last modification on : Tuesday, January 4, 2022 - 6:12:42 AM



Ilias Sourikopoulos, Andreia Cathelin, Andreas Kaiser, Antoine Frappé. Coarse/fine delay element design in 28 nm FD-SOI. The Fourth Terminal, Springer International Publishing, pp.119-134, 2020, Integrated Circuits and Systems book series (ICIR), ISBN 978-3-030-39495-0 ; eISBN 978-3-030-39496-7. ⟨10.1007/978-3-030-39496-7_6⟩. ⟨hal-03377034⟩



Les métriques sont temporairement indisponibles