Short-circuit robustness of parallel SiC MOSFETs and fail-safe mode strategy

François Boige (1, 2, 3) , Asad Fayyaz (4, 5) , Alberto Castellazzi (4, 5) , Frédéric Richardeau (1, 3) , Sébastien Vinnac (6, 7, 8, 9)

1 LAPLACE-CS - Convertisseurs Statiques
2 CNRS - Centre National de la Recherche Scientifique
3 University of Toulouse
4 Power Electronics Machines and Control (PEMC) Group
5 Faculty of Engineering [Nottingham]
6 LAPLACE - LAboratoire PLasma et Conversion d'Energie
7 ENSEEIHT - Ecole Nationale Supérieure d'Electrotechnique, d'Electronique, d'Informatique, d'Hydraulique et de Télécommunications
8 Toulouse INP - Institut National Polytechnique (Toulouse)
9 University of Toulouse

Silicon carbide (SiC) power MOSFETs exhibit some key differences compared with Silicon (Si) MOSFETs and IGBTs. In particular, both their intrinsic (i.e., material technology related) and extrinsic (i.e., device generation related) features-set implies, on the one hand, higher stress levels of the single chip during a short-circuit and, on the other hand, a greater spread in the value of some of the main electro-thermal parameters affecting the transistor performance during this stressful transient event. Thus, this paper proposes a thorough experimental analysis of the short-circuit robustness of parallel connected SiC Power MOSFETs, taking into account the actual distribution in their parameters. The overall aim is twofold: producing de-rating guidelines for multi-chip structures and developing validated strategies for ensuring new and original soft-fail (or fail-safe) modalities in the application, as a result of both single and repetitive pulse degradation.

Keywords: Silicon carbide (SiC); Wide bandgap devices; Power MOSFET; Short-circuit; Robustness; Parallel Operation

Domains: Electric power

François Boige, Asad Fayyaz, Alberto Castellazzi, Frédéric Richardeau, Sébastien Vinnac. Short-circuit robustness of parallel SiC MOSFETs and fail-safe mode strategy. European Power Elecrtonics and Applications 2019 - IEEE ECCE Europe, Sep 2019, Gênes, Italy. ⟨hal-02334405⟩