HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems

Abstract : Runtime verification provides a theoretical proved framework to synthesize monitors from formal specifications. At runtime, these monitors can be used to check that the execution of the system does not violate a security policy or a safety property. In this paper, we focus on the runtime verification of safety properties of real-time embedded software. For these systems, it must be ensured that monitoring does not jeopardize the scheduling. To do so, we use a hybrid hardwaresoftware approach in the context of System-on-Programmable- Chip. A minimal instrumentation is added to the software to extract the execution trace. The verification is performed by hardware monitors on the FPGA. This implementation makes it possible to obtain a temporal overhead almost as low as a hardware implementation while allowing the use of efficient off-the-shelf platforms. The paper describes the architecture, its implementation, and shows results on a realistic case study.
Type de document :
Poster
NASA/ESA Conference on Adaptive Hardware and Systems, Aug 2018, Edinburgh, United Kingdom. IEEE, 2018, AHS 2018. 〈https://www.ahs-conf.org/〉
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https://hal.archives-ouvertes.fr/hal-01804096
Contributeur : Sandrine Charlier <>
Soumis le : jeudi 31 mai 2018 - 13:29:49
Dernière modification le : vendredi 16 novembre 2018 - 01:31:01

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  • HAL Id : hal-01804096, version 1

Citation

Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement. HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems. NASA/ESA Conference on Adaptive Hardware and Systems, Aug 2018, Edinburgh, United Kingdom. IEEE, 2018, AHS 2018. 〈https://www.ahs-conf.org/〉. 〈hal-01804096〉

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