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HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems

Abstract : Runtime verification provides a theoretical proved framework to synthesize monitors from formal specifications. At runtime, these monitors can be used to check that the execution of the system does not violate a security policy or a safety property. In this paper, we focus on the runtime verification of safety properties of real-time embedded software. For these systems, it must be ensured that monitoring does not jeopardize the scheduling. To do so, we use a hybrid hardwaresoftware approach in the context of System-on-Programmable- Chip. A minimal instrumentation is added to the software to extract the execution trace. The verification is performed by hardware monitors on the FPGA. This implementation makes it possible to obtain a temporal overhead almost as low as a hardware implementation while allowing the use of efficient off-the-shelf platforms. The paper describes the architecture, its implementation, and shows results on a realistic case study.
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Contributor : Sandrine Charlier <>
Submitted on : Thursday, May 31, 2018 - 1:29:49 PM
Last modification on : Friday, January 8, 2021 - 3:43:09 AM



Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement. HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems. 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Aug 2018, Edinburgh, United Kingdom. ⟨10.1109/AHS.2018.8541459⟩. ⟨hal-01804096⟩



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