Validation of neural networks onto FPGA
Abstract
Recent works in artificial neural networks simulation showed that sizable networks, of the order of thousands of mammalian neurons, are now achievable. In the domain of microelectronics, rapid prototyping of complex hardware neural networks (hundreds) is still a major challenge for executing in real-time high-level cognitive tasks onto FPGAs. This paper addresses the related problem of validating these complex networks when the observation on the chip interface of the whole system, specially the high number of internal signals, is not feasible anymore. We present a validation methodology covering the different design steps, from high-level modeling and simulation to on-board level debugging.