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Conference Papers Year : 2014

Designing optimized parallel interleaver architecture through network customization

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Hardware Architecture [cs.AR] Signal and Image processing Signal and Image Processing

Cyrille Chavet  : Connect in order to contact the contributor

https://hal.science/hal-01009679

Submitted on : Wednesday, June 18, 2014-2:17:42 PM

Last modification on : Friday, March 24, 2023-2:52:59 PM

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hal-01009679 , version 1 (18-06-2014)

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  • HAL Id : hal-01009679 , version 1

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Cyrille Chavet, Philippe Coussy, Saeed Ur Reehman. Designing optimized parallel interleaver architecture through network customization. Colloque national du GdR SoC-SiP, Jun 2014, France. ⟨hal-01009679⟩

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