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Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic

Abstract : Field programmable gate arrays (FPGAs) become very popular for embedded cryptographic operations. In order to resist side-channel attacks, FPGAs must implement reasoned countermeasures. The most efficient way to mitigate attacks is to adopt a gate-level protection. Two secure gates families exist: those that ``hide'' and those that ``mask'' side-channel leakage. In this article, we detail methods to reduce the size of wave dynamic differential logic (WDDL) implementations. These circuits are designed to hide any physical leak by ensuring a data-independent activity. This study is meant to be generic, and thus applies to any $4 \to 1$ LUT-based FPGAs. Further optimizations can be reached by taking advantage of some FPGAs proprietary features. Our solutions include RTL code modification, synthesizer usage (potentially in a re-entrant way), and ad hoc mapping. For the first time, we point out how sequential parts (e.g. registers) of the design can participate to the overall area savings. Also, we show that linear parts of algorithms can be delegated to a synthesizer, but that non-linear parts are better off to be handled with heuristics. We present a 23% area gain over the state-of-the-art as for the positive WDDL triple-DES symmetric encryption algorithm.
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Contributor : Sylvain Guilley Connect in order to contact the contributor
Submitted on : Sunday, March 1, 2009 - 6:19:41 PM
Last modification on : Thursday, November 18, 2021 - 1:02:05 PM
Long-term archiving on: : Wednesday, September 22, 2010 - 12:23:50 PM


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Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst. Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic. International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.161-166, ⟨10.1109/FPL.2008.4629925⟩. ⟨hal-00320425v2⟩



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