High frequency low noise potentialities of down to 65nm technology nodes MOSFETs

Gilles Dambrine (1) , Daniel Gloria (2) , Patrick Scheerer (2) , Christine Raynaud (2) , Francois Danneville (1) , Sylvie Lepilliet (1) , Alexandre Siligaris (1) , Guillaume Pailloncy (1) , Baudouin Martineau (1, 2) , Emmanuel Bouhana (1, 2) , Raphael Valentin (1)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 ST-CROLLES - STMicroelectronics [Crolles]

65 nm n-MOSFETs show state-of-the-art cut-off frequency with f t = 210 GHz and microwave low noise and high gain properties (NF min = 0.8 dB and G ass = 17.3 dB at 12 GHz). As compared with the previous nodes, the high frequency properties of these MOSFETs continue to be in agreement with the downscaling trends.

Mots clés: CMOS technology; MOSFET circuits; Millimeter wave technology; Transconductance; Calibration; Cutoff frequency; Microwave technology; Microelectronics

Domaines: Sciences de l'ingénieur [physics]

Gilles Dambrine, Daniel Gloria, Patrick Scheerer, Christine Raynaud, Francois Danneville, et al.. High frequency low noise potentialities of down to 65nm technology nodes MOSFETs. European Gallium Arsenide and Other Semiconductor Application Symposium, GAAS 2005, Oct 2005, Paris, France. pp.97-100. ⟨hal-00125303⟩