Gals systems prototyping using multiclock fpgas and asynchronous network-on-chips
Résumé
This paper presents an innovating methodology for network-centric Globally-Asynchronous Locally-Synchronous (GALS) system prototyping. High-performance multi-clock FPGAs are exploited for easy and fast prototyping of GALS systems based of an Asynchronous Network-on-Chip (ANoC) interfacing synchronous standard IP cores. Modularity property of asynchronous circuits is fully exploited to design regular distributed interconnect topologies by the means of basic topology-free building blocks, with a focus and special design effort to solve arbitration and synchronization problems. A case-study is implemented on an up-to-date FPGA which includes two independently clocked processors, memory banks, serial and parallel communication links and an asynchronous DES (Data Encryption Standard) module connected through an asynchronous 5x5 crossbar. The clock-less modules are implemented using a quasi-delay insensitive logic on the FPGA by the means of a dedicated library. Performance figures are reported on the FPGA platform, especially for communication costs, speed and latency of the ANoC.