Efficient design and programming of Multiple Processors System on Chip architectures

Abstract : The embedded applications come up with more and more functionalities inducing various kinds of computation to realize. The major impact of these new application needs is the steadily evolution of the embedded systems performances in terms of computing power and memory capacity. These systems have to find a trade-off between their capacity (computing power, dynamicity) and the embedded system constraints (silicium, consumption). To face these hard constraints MPSoC architectures have appeared as a major promoter of the industrial revolution of semiconductors. However, designing a low power MPSoC architecture, supporting the required performance is not easy. This balance depends on the effects of various parameters such as the number of cores, the overall energy envelope, the type of interconnection network, the architecture of the memory hierarchy, the deployment of the application on the system. All these challenges during the definition of MPSoC architectures spotlight the needs of an automatic design process to help the user design and program these architectures. In the context of this thesis our contributions is the definition of a design space exploration methodology. This methodology aims to define a hardware architecture and the associated executable binary code based on three inputs: (1) An application C code, (2) An architecture library and (3) A constraints file. Moreover because we aims to explore and generates hardware architectures our second contribution is the definition of two hardware modules. The first hardware module defines a hardware memory management unit used to ease the programming of the MPSoC architectures and increase their performances. The second hardware module is the accelerator interface which is used to abstract the heterogeneity of the heterogeneous MPSoC architectures, ease their definition and programming.
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  • HAL Id : tel-01104791, version 1

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Romain Brillu. Efficient design and programming of Multiple Processors System on Chip architectures. Engineering Sciences [physics]. UNIVERSITE DE NANTES, 2014. English. ⟨tel-01104791⟩

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