Power management through DVFS and dynamic body biasing in FD-SOI circuits

Yeter Akgul (1) , Diego Puschini (1) , Suzanne Lesecq (1) , Edith Beigné (1) , Ivan Miro-Panades (1) , Pascal Benoit (2) , Lionel Torres (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 SysMIC - Conception et Test de Systèmes MICroélectroniques

The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.

Mots clés: FD-SOI circuit; Digital Signal Processor

Domaines: Micro et nanotechnologies/Microélectronique

Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro-Panades, et al.. Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC: Design Automation Conference, Jun 2014, San Francisco, United States. pp.1-6, ⟨10.1145/2593069.2593185⟩. ⟨lirmm-01421009⟩