Defect Analysis in Power Mode Control Logic of Low-Power SRAMs

Leonardo B. Zordan (1) , Alberto Bosio (1) , Luigi Dilillo (1) , Patrick Girard (1) , Aida Todri-Sanial (1) , Arnaud Virazel (1) , Nabil Badereddine (2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 IMC - Intel Mobile Communications

Summary form only given. Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches.

Mots clés: low-power design; memory test; power mode control logic; power switch; failure analysis; SRAM

Domaines: Electronique

Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Defect Analysis in Power Mode Control Logic of Low-Power SRAMs. ETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233033⟩. ⟨lirmm-00805374⟩