SoC Yield Improvement: Redundant Architectures to the Rescue

Julien Vial (1) , Alberto Bosio (2) , Patrick Girard (2) , Christian Landrault (1) , Serge Pravossoudovitch (2) , Arnaud Virazel (2)

1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.

Domaines: Micro et nanotechnologies/Microélectronique

Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. SoC Yield Improvement: Redundant Architectures to the Rescue. ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.7, 2008. ⟨lirmm-00341799⟩