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Journal articles
Some Optimizations of Hardware Multiplication by Constant Matrices
Abstract : This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.
Cited literature [26 references]
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00113092
Contributor : Arnaud Tisserand <>
Submitted on : Friday, November 10, 2006 - 3:31:42 PM
Last modification on : Thursday, November 21, 2019 - 2:28:35 AM
Long-term archiving on: : Tuesday, April 6, 2010 - 7:23:31 PM
Contributor : Arnaud Tisserand <>
Submitted on : Friday, November 10, 2006 - 3:31:42 PM
Last modification on : Thursday, November 21, 2019 - 2:28:35 AM
Long-term archiving on: : Tuesday, April 6, 2010 - 7:23:31 PM