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Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Abstract : Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual- issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
Cited literature [21 references]
https://hal.inria.fr/inria-00585320
Contributor : Florian Brandner Connect in order to contact the contributor
Submitted on : Tuesday, April 12, 2011 - 3:19:01 PM
Last modification on : Thursday, January 20, 2022 - 4:15:46 PM
Long-term archiving on: : Thursday, November 8, 2012 - 4:11:41 PM
Contributor : Florian Brandner Connect in order to contact the contributor
Submitted on : Tuesday, April 12, 2011 - 3:19:01 PM
Last modification on : Thursday, January 20, 2022 - 4:15:46 PM
Long-term archiving on: : Thursday, November 8, 2012 - 4:11:41 PM
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schoeberl-ppes11.pdf
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