Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

J.A. Clemente (1) , F.J. Franco (2) , Francesca Villa (3) , Maud Baylac (3) , Pablo Francisco Ramos Vargas (4) , Vanessa Carolina Vargas Vallejo (4) , H. Mecha (2) , J.A. Agapito (2) , Raoul Velazco (5)

1 Department of Computer Architecture and Automation [Madrid]
2 Departamento de Fisica Aplicada [UCM Madrid]
3 LPSC - Laboratoire de Physique Subatomique et de Cosmologie
4 ESPE - Universidad de las Fuerzas Armadas [Sangolqui]
5 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Mots clés: SRAM; neutron; SEU; Power

Domaines: Micro et nanotechnologies/Microélectronique; Physique des accélérateurs [physics.acc-ph]

J.A. Clemente, F.J. Franco, Francesca Villa, Maud Baylac, Pablo Francisco Ramos Vargas, et al.. Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons. Conference on Radiation and its Effects on Components and Systems (RADECS), Sep 2015, Moscow, Russia. pp.2072-2079, ⟨10.1109/TNS.2016.2522819⟩. ⟨in2p3-01391224⟩