The FE-I4 Pixel Readout Integrated Circuit

M. Garcia-Sciveres , D. Arutinov , M. Barbero , R. Beccherle , S. Dube , D. Elledge , J. Fleury (1) , D. Fougeron (2) , F. Gensolen (2) , D. Gnani , V. Gromov , T. Hemperek , M. Karagounis , R. Kluit , A. Kruth , A. Mekkaoui , M. Menouni (2) , J.-D. Schipper

1 LAL - Laboratoire de l'Accélérateur Linéaire
2 CPPM - Centre de Physique des Particules de Marseille

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

Mots clés: Pixel detector; ATLAS upgrades; High luminosity; 130 nm

Domaines: Electronique; Micro et nanotechnologies/Microélectronique

M. Garcia-Sciveres, D. Arutinov, M. Barbero, R. Beccherle, S. Dube, et al.. The FE-I4 Pixel Readout Integrated Circuit. 7th International ""Hiroshima"" Symposium on the Development and Application of Semiconductor Tracking Detectors, Aug 2009, Hiroshima, Japan. pp.S155-S159, ⟨10.1016/j.nima.2010.04.101⟩. ⟨in2p3-00479837⟩