Extended RISC-V hardware architecture for future digital communication systems

Mael Tourres , Bertrand Le Gal , Jeremie Crenne , Philippe Coussy , Cyrille Chavet (1, 2)

1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
2 Lab-STICC_UBS_CACS_MOCS

The fast deployment of IoT (Internet-of-Things) devices for a few years has been impressive and the progressive deployment of 5G will accelerate things even further. Indeed, this standard opens the door to a new generation of standards aiming at a convergence of networks and communication protocols (Wi-fi, LTE, 4G, etc.). These results in the need for flexible implementations of different families of codes as for instance, Turbo, LPDC and Polar codes. In this context, the work presented in this article proposes to design such flexible ASIP (application-specific instruction set processor) in an IoT context. The approach discussed is supported by experimental results obtained on the basis of a RISC-V architecture to which specific instruction sets have been added. Results demonstrate a reduction of the required processing clock cycles up to 47.7%, 29.8%, 16.5% and 9.7% for Polar, LDPC, NB-LDPC and Turbo (LTE) codes, respectively.

Mots clés: IoT devices; Forward Error Correction codes; 4G; 5G; ASIP; RISC-V; IoT devices

Domaines: Architectures Matérielles [cs.AR]; Systèmes embarqués; Traitement du signal et de l'image [eess.SP]; Réseau de neurones [cs.NE]; Ingénierie assistée par ordinateur

Mael Tourres, Bertrand Le Gal, Jeremie Crenne, Philippe Coussy, Cyrille Chavet. Extended RISC-V hardware architecture for future digital communication systems. 2021 IEEE 4th 5G World Forum (5GWF), Oct 2021, Montreal, Canada. pp.224-229, ⟨10.1109/5GWF52925.2021.00046⟩. ⟨hal-03586276⟩