Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

Yazan Barazi (1, 2, 3, 4, 5) , Frédéric Richardeau (5, 3) , Nicolas C. Rouger (5) , Jean-Marc Blaquière (5, 2, 3, 4)

1 LAPLACE - LAboratoire PLasma et Conversion d'Energie
2 CNRS - Centre National de la Recherche Scientifique
3 Toulouse INP - Institut National Polytechnique (Toulouse)
4 UT - Université de Toulouse
5 LAPLACE-CS - Convertisseurs Statiques

This paper focuses on the extensive robustness validation of a gate charge detection method designed for SiC MOSFETs under short-circuit operation, and, in terms of failure-modes. The benefits of having a fast (submicrosecond-150ns) detection method is illustrated by a 1D thermo-metallurgical simulation. This method is integrated owing to an optimized SMD/PCB technology (Surface-Mount Device/ Printed Circuit Board).

Domaines: Energie électrique

Yazan Barazi, Frédéric Richardeau, Nicolas C. Rouger, Jean-Marc Blaquière. Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device. 32th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 2021, Oct 2021, Bordeaux, France. ⟨hal-03371958⟩