Power-efficient reliable register file for aggressive-environment applications

Ihsen Alouani (1, 2, 3, 4) , Hamzeh Ahangari (5) , Özcan Özturk (5) , Smail Niar (6)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 COMNUM - IEMN - COMmunications NUMériques - IEMN
3 IEMN-DOAE - Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520
4 INSA Hauts-De-France - INSA Institut National des Sciences Appliquées Hauts-de-France
5 Bilkent University [Ankara]
6 LAMIH - Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201

In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors' results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.

Mots clés: embedded systems; microprocessor chips; integrated circuit reliability; power aware computing; floating point arithmetic; reliability; flip-flops; power-efficient reliable register file; aggressive-environment applications; on-board data processing; reduced power budget; serious design challenge; embedded system manufacturers; embedded processors; aggressive environments; error hardening; critical element; processor pipeline; fault immune computing systems; authors propose; RF architecture; adjacent byte-level narrow-width values; integer registers; nonutilised bits; counterpart register; floating point critical bits; low power budget; normal operating conditions; highly aggressive operating conditions; floating point RF reliability enhancement techniques; adjacent register hardened RF

Domaines: Sciences de l'ingénieur [physics]; Informatique [cs]; Intelligence artificielle [cs.AI]; Réseaux et télécommunications [cs.NI]; Traitement du signal et de l'image [eess.SP]; Electronique

Ihsen Alouani, Hamzeh Ahangari, Özcan Özturk, Smail Niar. Power-efficient reliable register file for aggressive-environment applications. IET Computers & Digital Techniques, 2020, 14 (1), pp.1-8. ⟨10.1049/iet-cdt.2018.5047⟩. ⟨hal-03322796⟩