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A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory

Abstract : We study the implementation of dataflow applications on multi-core processor with on-chip shared multi-banked memory. Specifically, we consider the Kalray MPPA2 processor and three applications coded using the industrial toolchain SCADE Suite. We focus on the runtime environment assuming global static scheduling, time-triggered and non-preemptive execution of tasks. Our contributions include (i) a technique to implement SCADE applications compliant with execution models inspired by PREMs (PRedictable Execution Models), (ii) an exhaustive comparison of three execution models with and without isolation, and finally (iii) guidelines for predictable implementation of a data-flow application on multi-core processors with shared on-chip memory.
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https://hal.archives-ouvertes.fr/hal-03185800
Contributor : Matheus Schuh Connect in order to contact the contributor
Submitted on : Tuesday, March 30, 2021 - 3:59:40 PM
Last modification on : Wednesday, November 3, 2021 - 6:18:42 AM

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Matheus Schuh, Claire Maïza, Joël Goossens, Pascal Raymond, Benoît Dupont de Dinechin. A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. 2020 IEEE Real-Time Systems Symposium (RTSS), Dec 2020, Houston, TX, United States. ⟨10.1109/RTSS49844.2020.00034⟩. ⟨hal-03185800⟩

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