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Conference papers

Verification and synthesis using real quantifier elimination

Thomas Sturm 1, 2, 3 Ashish Tiwari 4
1 VERIDIS - Modeling and Verification of Distributed Algorithms and Systems
LORIA - FM - Department of Formal Methods , Inria Nancy - Grand Est, MPII - Max-Planck-Institut für Informatik
2 MOSEL - Proof-oriented development of computer-based systems
LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
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Submitted on : Tuesday, February 16, 2021 - 1:46:45 PM
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Thomas Sturm, Ashish Tiwari. Verification and synthesis using real quantifier elimination. Proc. ISSAC 2011, Jun 2011, San Jose, United States. pp.329, ⟨10.1145/1993886.1993935⟩. ⟨hal-03142063⟩



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