Recommendations for a radically secure ISA

Mathieu Escouteloup (1, 2, 3) , Ronan Lashermes (4, 5) , Jean-Louis Lanet (5) , Jacques Jean-Alain Fournier (6, 7, 8)

1 CNRS - Centre National de la Recherche Scientifique
2 UR - Université de Rennes
3 CIDRE - Confidentialité, Intégrité, Disponibilité et Répartition
4 SED [Rennes] - Service Expérimentation et Développement
5 LHS - Inria - Laboratoire de Haute Sécurité
6 UGA - Université Grenoble Alpes
7 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
8 DSYS - Département Systèmes

The rising number of attacks targeting processors at micro-architecture level encourages more research on hardware level solutions. In this position paper, we specify a new RV32S “secure” instruction set architecture (ISA) derived from the RV32I RISC-V ISA. We propose modifications in the ISA to prevent timing side-channels, strengthen control flow integrity and ensure micro-architectural state isolation. The goal is to provide a new minimal hardware/software approach through which software attacks exploiting hardware vulnerabilities can be circumvented.

Mots clés: Side-channels; Hardware Security Context; Instruction Set Architecture

Domaines: Architectures Matérielles [cs.AR]; Cryptographie et sécurité [cs.CR]

Mathieu Escouteloup, Ronan Lashermes, Jean-Louis Lanet, Jacques Jean-Alain Fournier. Recommendations for a radically secure ISA. CARRV 2020 - Workshop on Computer Architecture Research with RISC-V, May 2020, Valence (virtual), Spain. pp.1-22. ⟨hal-03128242⟩