Design, Fabrication and Characterization of Surface Electrode Ion Trap Integrated with TSV

Peng Zhao (1) , Jing Tao (1) , Hong Yu Li , Yu Dian Lim (1) , Luca Guidoni (2) , Chuan Seng Tan (1)

1 Nanyang Technological University [Singapour]
2 MPQ (UMR_7162) - Laboratoire Matériaux et Phénomènes Quantiques

Further miniaturization of surface electrode ion trap is restricted by wire bonding connection. To resolve this restriction, integration of conventional surface electrode ion trap with through silicon via (TSV) interconnects is proposed and preliminarily demonstrated. Located directly underneath the DC and RF electrodes, TSVs can transmit the electrical signal from interposer to the electrodes on the top. In this work, electrostatic simulation and fabrication processes are introduced to justify the feasibility of this integration. From the electrical characterization (I-V and C-V tests) results, TSV-integrated ion trap exhibits smaller leakage current and lower capacitance than its wire bonding counterparts due to the elimination of large surface area

Domaines: Micro et nanotechnologies/Microélectronique; Physique Quantique [quant-ph]

Peng Zhao, Jing Tao, Hong Yu Li, Yu Dian Lim, Luca Guidoni, et al.. Design, Fabrication and Characterization of Surface Electrode Ion Trap Integrated with TSV. IEEE 21st Electronics Packaging Technology Conference (EPTC 2019), Dec 2019, Singapour, Singapore. pp.13-17, ⟨10.1109/EPTC47984.2019.9026716⟩. ⟨hal-03066897⟩