A Cascaded Gate Driver Architecture to Increase the Switching Speed of Power Devices in Series Connection
Résumé
This paper presents a cascaded gate driver architecture to improve the switching speed of series-connected power devices. The main idea is to propose a new technique to increase the dV /dt of the devices when their voltages are already balanced. In complex power converters like multi-cell and multi-level topologies, and series-connected power devices, many driver circuits are required and implemented. In such converters, there are several dV /dt sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (supplies and control signal isolation units), which can amplify the conducted electromagnetic interference (EMI) perturbations and therefore the switching speed of the power devices can be affected. This paper is focused on the analysis of a new cascaded configuration of gate drivers to increase the switching speed, and consequently reducing the switching losses of the series-connected transistor topologies. This improvement is achieved by reducing the equivalent parasitic capacitance of the gate driver circuitry considering the gate driver architectures: a new concept of Cascaded Gate Driver is presented. Theoretical and experimental measurements are used to support the Cascade Gate Driver Architecture proposed in this paper.
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