A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC
Résumé
Fast yet accurate performance and timing prediction of complex
parallel data flow applications on multi-processor systems remains
a difficult discipline. The reason for it comes from the complexity of
the data flow applications and the hardware platform with shared
resources, like buses and memories. This combination may lead to
complex timing interferences that are difficult to express in pure analytical
or classical simulation-based approaches. In this work, we
propose a message-level communication model for timing and performance
prediction of Synchronous Data Flow (SDF) applications
on MPSoCs with shared memories. We compare our work against
measurement and TLM simulation-based performance prediction
models on two case-studies from the computer vision domain. We
show that the accuracy and execution time of our simulation outperforms
existing approaches and is suitable for a fast yet accurate
design space exploration.