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La décimation des convertisseurs Sigma-Delta

Hassan Aboushady 1
1 ASIM - Architecture des Systèmes intégrés et Micro électronique
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : Nowadays, Sigma-Delta is a widely known technique for Analog-to-Digital conversion. This stems from the fact that Sigma-Delta Analog-to-Digital converters can easily be integrated in digital VLSI technologies. Nevertheless, this conversion technique requires digital post-processing in order to transform the 1-bit output of the analog modulator, sampled at a frequency of OSR_Fn, to N-bits, sampled at the Nyquist rate Fn. While the performance of the Sigma-Delta converter (resolution and speed) is usually determined by the analog modulator, the area and power consumption of the decimation filter are crucial for the overall A/D converter. The order and the number of operations per seconde of this decimation filter is very high. This is due to the very high sampling frequency and the very narrow transition-band required in this filter. Multi-rate Multi-stage structure can significantly reduce the required number of operation per second. In the first stages, where the sampling frequency is very high, we use filters with large transition-bands. In the last stages, the sampling frequency is much lower and filters with narrow transition-bands can easily be realized. In this report, we present the different decimation filter stages. The design method and the simulation of these filters are detailed. We also present filter architectures optimized for silicon implementation.
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  • HAL Id : hal-02548416, version 1

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Hassan Aboushady. La décimation des convertisseurs Sigma-Delta. [Rapport de recherche] lip6.1997.041, LIP6. 1997. ⟨hal-02548416⟩

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