A 5-Gbps FPGA prototype of a (31,29)2 Reed-Solomon Turbo Decoder

Camille Leroux (1) , Gérald Le Mestre (2, 1) , Christophe Jego (2, 1) , Patrick Adde (2, 1) , Michel Jezequel (2, 1)

1 ELEC - Département Electronique
2 Lab-STICC_TB_CACS_IAS

In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra highspeed context. A full-parallel architecture dedicated to the turbo decoding process of RS product codes is described. An experimental setup composed of a Dinigroup board that includes six Xilinx Virtex-5 LX330 FPGAs is employed. Thus, a full-parallel turbo decoding architecture dedicated to the (31, 29)2 RS product code has been designed and then implemented into a 5Gbps experimental setup. The purpose of this prototype is to demonstrate that RS turbo decoders can effectively achieve information rates above 1Gbps. The results show that the RS turbo product codes offer a good complexity/performance trade off for ultra-high throughputs. The major limitation in terms of data rate of our prototype is the data exchange between the FPGAs of the board. Indeed, the turbo decoder architecture enables decoding at information rates until 10Gbps onto FPGA devices.

Mots clés: Turbo code; Implementation; Decoder; High data rate

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

Camille Leroux, Gérald Le Mestre, Christophe Jego, Patrick Adde, Michel Jezequel. A 5-Gbps FPGA prototype of a (31,29)2 Reed-Solomon Turbo Decoder. 5th International Symposium on Turbo Codes and Related Topics, Sep 2008, Lausanne, Switzerland. pp.12. ⟨hal-02194897⟩