Reducing timing interferences in real-time applications running on multicore architectures

Abstract : We introduce a unified wcet analysis and scheduling framework for real-time applications deployed on multicore architectures. Our method does not follow a particular programming model, meaning that any piece of existing code (in particular legacy) can be re-used, and aims at reducing automatically the worst-case number of timing interferences between tasks. Our method is based on the notion of Time Interest Points (tips), which are instructions that can generate and/or suffer from timing interferences. We show how such points can be extracted from the binary code of applications and selected prior to performing the wcet analysis. We then represent real-time tasks as sequences of time intervals separated by tips, and schedule those tasks so that the overall makespan (including the potential timing penalties incurred by interferences) is minimized. This scheduling phase is performed using an Integer Linear Programming (ilp) solver. Preliminary results on state-of-the-art benchmarks show promising results and pave the way for future extensions of the model and optimizations.
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  • HAL Id : hal-02181900, version 1
  • OATAO : 22540

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Thomas Carle, Hugues Cassé. Reducing timing interferences in real-time applications running on multicore architectures. 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018), Jul 2018, Barcelone, Spain. pp.1-11. ⟨hal-02181900⟩

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