Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

R. Silveira Feitoza (1) , Manuel J. Barragan (1) , Salvador Mir (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

Domaines: Micro et nanotechnologies/Microélectronique

R. Silveira Feitoza, Manuel J. Barragan, Salvador Mir. Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2019, Cuzco, Peru. pp.263-268, ⟨10.1109/VLSI-SoC.2019.8920377⟩. ⟨hal-02165220⟩