Architectural exploration of hardware Spiking Neural Networks integrating Non-Volatile Memories
Résumé
A simulator for hardware Spiking Neural Networks have been developed, in order to evaluate different implementation architectures in terms of processing latency, energy consumption, and chip surface. This simulator integrates different types of architectures, memory units distribution and memory technologies, in order to find which configuration would suit the
best to intelligent and autonomous embedded systems. Our simulator is a first step into architectural exploration of Spiking Neural Network implementations, as it brings coarse but coherent estimations for five different possible hardware
architectures. Estimations for all available architectures on an example network are given, and we show how they seem coherent when compared with each other. Lastly, some additions and modifications are still to be done in order to achieve a better accuracy and reliability of latency, surface and energy consumption estimations.