Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons

Hanen Chenini 1, 2 Jean Pierre Dérutin 2 Romuald Aufrère 2 Roland Chapuis 2
1 Lab-STICC_UBO_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
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https://hal.archives-ouvertes.fr/hal-02115059
Contributor : Romuald Aufrere <>
Submitted on : Tuesday, April 30, 2019 - 9:44:49 AM
Last modification on : Wednesday, May 1, 2019 - 1:36:22 AM

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Hanen Chenini, Jean Pierre Dérutin, Romuald Aufrère, Roland Chapuis. Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons. EURASIP Journal on Advances in Signal Processing, SpringerOpen, 2013, 2013 (1), ⟨10.1186/1687-6180-2013-153⟩. ⟨hal-02115059⟩

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