Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications

G. Molas (1) , Marc Bocquet (2) , J. Buckley (1) , J. P Colonna (1) , L. Masarotto , H. Grampeix (1) , F. Martin (1) , V. Vidal (1) , A. Toffoli (1) , P. Brianceau , L. Vermande (1) , P. Scheiblin (1) , M. Gély (1) , A. Papon (1) , G. Auvert (1) , L. Perniola (1) , C. Licitra (1) , T. Veyron (1) , N. Rochat (1) , C. Bongiorno (3) , S. Lombardo (3) , B. de Salvo (1) , S. Deleonibus (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
3 IMM - Istituto per la Microelettronica e Microsistemi [Catania]

In this paper we show for the 1 st time that Silicon nanocrystal (Si-ncs) memories with high-k (HfO2, Al2O3 and HfAlO) interpoly dielectrics (IPD) can offer excellent behaviour in the Fowler-Nordheim regime, with great relevance for future sub-45nm NAND memory generations. We significantly advance the state-of-the-art by showing a strict correlation between the different IPD properties (high-k dielectric constants, leakage currents) and the performance obtained on memory transistors down to 90nm gate lengths. In particular the results demonstrate that HfAlO IPDs combine the fast p/e and good 10 5 cycles endurance behaviour of HfO2 and the long retention of Al2O3 with no activation up to 125°C. Then, in order to boost the memory window, we also integrated a hybrid Si-nc/SiN layer floating gate, with a HfAlO based IPD. It is shown that a 6V Vth can be achieved, with good retention and cycling behaviours. Finally, a physical model of Si-nc memories is introduced which explains the impacts of IPD characteristics on memory performance. Introduction The large success of mobile equipment is leading to a dramatic increase of the market for NAND Flash, key devices for mass data storage [1]. Discrete trap memories, such as TANOS [2] and Si-nc memories [3,4] are one of the most suitable candidates to push integration density further beyond the 45nm node, because of their good scalability, robustness against SILC and low floating gate (FG) to floating gate coupling. In particular, Si-nc memories offer the potential of better data-retention at high temperature (the stored electrons being trapped in the Si-nc energy conduction band, rather than in temperature-activated deep traps of nitride), as well as mitigated lateral charge migration (the Si-ncs being isolated from one to the other by silicon dioxide rather than nitride). However, up to now, Si-nc memories have always shown poor FN program/erase characteristics, due to the small Si-nc/control gate coupling. In order to overcome this issue, engineering of the tunnel dielectric and/or IPD [5, 6] is necessary. In particular, in this paper, we present for the 1 st time to our knowledge an exhaustive experimental and theoretical study of Si-nc memories where the conventional HTO or oxide/nitride/oxide (ONO) interpoly dielectric is replaced by HfO2, Al2O3 or HfAlO based IPD. Excellent performance and clear correlations between the device electrical results and the IPD material properties are shown. We also suggest how to solve another issue of Si-nc devices, which makes them poorly interesting for multi-level NAND applications, i.e. the relatively small programming window. As a possible solution we propose the addition of a thin SiN layer over the Si-ncs, which allows for a significant increase of the memory window. Our approach is widely validated through in-depth analysis of Si-nc memories with HfO2, Al2O3 or HfAlO IPD, based on several material results, electrical data on memory transistors, physical modelling and TCAD three-dimensional simulations.

Domaines: Micro et nanotechnologies/Microélectronique

G. Molas, Marc Bocquet, J. Buckley, J. P Colonna, L. Masarotto, et al.. Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications. 2007 IEEE International Electron Devices Meeting - IEDM '07, Dec 2007, Washington, France. pp.453-456, ⟨10.1109/IEDM.2007.4418971⟩. ⟨hal-02072903⟩