High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

L. Pasini (1, 2, 3) , P. Batude (1) , M. Cassé (1) , B. Mathieu (1) , B. Sklenard (1) , F. Piegas Luce (1) , S. Reboh (1) , N. Bernier (1) , C. Tabone (1) , O. Rozeau (1) , S. Martini (1) , C. Fenouillet-Beranger (1) , L. Brunet (1) , G. Audoit (1) , D. Lafond (1) , F. Aussenac (1) , F. Allain (1) , G. Romano (2) , S. Barraud (1) , N. Rambal (1) , V. Barral (1) , L. Hutin (1) , J.M. Hartmann (1) , P. Besson (2) , S. Kerdiles (1) , M. Haond (2) , G. Ghibaudo (3) , M. Vinet (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]
3 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation

3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.

Domaines: Micro et nanotechnologies/Microélectronique

L. Pasini, P. Batude, M. Cassé, B. Mathieu, B. Sklenard, et al.. High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator. 2015 IEEE Symposium on VLSI Technology, Jun 2015, Kyoto, Japan. pp.T50-T51, ⟨10.1109/VLSIT.2015.7223699⟩. ⟨hal-02049770⟩