Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance

Lama Rahhal (1, 2) , Guillaume Bertrand (1) , Aurélie Bajolet (1) , Julien Rosa (1) , Gérard Ghibaudo (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation

The work presented in this paper investigates the possibility of replacing a Lateral Drain Extended MOS (LDEMOS) SOI transistors by a cascode configuration to improve the electrical mismatch performance. The cascode connection of two MOS devices is known to sustain as high drain voltage as LDEMOS SOI transistors and offers the same mismatch robustness of Silicon On Insulator (SOI) MOS transistors. The individual mismatch constants associated to Vt (iA Δvt ), β (iA Δβ/β ) and Id (iA ΔId/Id ) for the presented cascode configuration are shown to have similar values to those reported for individual MOS devices.

Mots clés: Lateral Drain Extended MOS (LDEMOS); SOI transistors; individual mismatch constants; mismatch; cascode configuration; drain voltage

Domaines: Micro et nanotechnologies/Microélectronique

Lama Rahhal, Guillaume Bertrand, Aurélie Bajolet, Julien Rosa, Gérard Ghibaudo. Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance. 2014 International Conference on Microelectronic Test Structures (ICMTS), Mar 2014, Udine, Italy. pp.238-242, ⟨10.1109/ICMTS.2014.6841499⟩. ⟨hal-02049001⟩