A Neural Model for RT-Level Power Estimation on FPGAs

Yehya Nasser (1) , Jean-Christophe Prevotet (2) , Maryline Hélard (3)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 INSA Rennes - Institut National des Sciences Appliquées - Rennes
3 FT R&D - France Télécom Recherche & Développement

Power optimization is required all along the design flow but particularly in the first steps where it has the strongest impact. In this work, we propose new power models based on neural networks that predict the power consumed by digital operators implemented on Field Pro-grammable Gate Arrays (FPGAs). These operators are interconnected and the statistical information of data patterns are propagated among them. The obtained results make an overall power estimation of a specific design possible. A comparison is performed to evaluate the accuracy of our power models against the estimations provided by the Xilinx Power Analyzer (XPA) tool. Our approach is verified at system-level where different processing systems are implemented. A mean absolute percentage error which is less than 8% is shown versus the Xilinx classic flow dedicated to power estimation.

Domaines: Sciences de l'ingénieur [physics]

Yehya Nasser, Jean-Christophe Prevotet, Maryline Hélard. A Neural Model for RT-Level Power Estimation on FPGAs. 13ème Colloque du GDR SoC/SiP 2018, Jun 2018, Paris, France. ⟨hal-02021099⟩