Novel Fine-Grain Back Bias Assist Techniques for 14 nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic

D. Bosch (1) , François Andrieu (1) , Lorenzo Ciampolini (2) , Adam Makosiej (1) , Olivier Weber (1) , Xavier Garros (1) , Joris Lacord (1) , Jacques Cluzel (1) , E. Esmanhotto , M. Rios , S. Lang , B. Giraud , Rémy Berthelon (3) , Gérald Cibrario (1) , Laurent Brunet (1) , Perrine Batude (1) , Claire Fenouillet-Beranger (1) , D. Lattard (1) , J.P. Colinge (1) , Francis Balestra (4) , Maud Vinet (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 STMicroelectronics
3 ST-CROLLES - STMicroelectronics [Crolles]
4 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) 0.078µm 2 SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV at 6w.r.t. planar SRAMs.

Domaines: Micro et nanotechnologies/Microélectronique

D. Bosch, François Andrieu, Lorenzo Ciampolini, Adam Makosiej, Olivier Weber, et al.. Novel Fine-Grain Back Bias Assist Techniques for 14 nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic. 2019 International Symposium on VLSI Technology, Systems and Applications (2019 VLSI-TSA), Apr 2019, Taiwan, China. ⟨hal-02015950⟩