Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes

L. Gaben (1, 2, 3) , V. Balan (2) , C. Euvrard (2) , S. Pauliac (2) , J.-A. Dallery (2, 4) , J. Bustos (1, 2) , R. Dechanoz (2) , B. Hemard (1) , L. Koscianski (2) , X. Bossy (2, 1) , C. Arvet (1, 2) , C. Vizioz (2) , S. Barnola (2) , C. Perrot (1, 2) , J. Sturm (2) , Y. Exbrayat (2) , V. Loup (2) , P. Besson (2) , B. Perrin (2) , B. Previtali (2) , P. Samson (1) , S. Barraud (2) , S. Monfray (1) , F. Boeuf (1) , T. Skotnicki (1) , F. Balestra (3) , M. Vinet (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
4 Vistec Electron Beam GmbH

Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

Mots clés: stacked nanowire FETs; HSQ; FinFET; SNWFET; 3D lithography

Domaines: Micro et nanotechnologies/Microélectronique

L. Gaben, V. Balan, C. Euvrard, S. Pauliac, J.-A. Dallery, et al.. Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.120-123, ⟨10.1109/ULIS.2017.7962617⟩. ⟨hal-02014232⟩