Low temperature junction formation by solid phase epitaxy on thin film devices: Atomistic modeling and experimental achievements

B. Sklenard (1) , P. Batude (1) , L. Pasini (1) , C. Fenouillet-Beranger (1) , B. Previtali (1) , M. Cassé (1) , L. Brunet (1) , P. Rivallin (1) , C. Barbé , C. Tavernier (2) , S. Cristoloveanu (3) , M. Vinet (1) , I. Martin-Bragado (4)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]
3 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
4 Institute IMDEA Materials [Madrid]

In this paper, we address the problem of junction formation with a low temperature processing (≤ 600°C) through Solid Phase Epitaxial Regrowth. We present the main experimental achievements and suggest solutions to optimize the junctions. In particular, atomistic simulations based on kinetic Monte Carlo (kMC) method allow getting insight into the complex physical phenomena that take place during junction formation.

Mots clés: Monte Carlo methods; thin film devices; solid phase epitaxial growth; silicon-on-insulator; semiconductor junctions; optimisation; low-temperature techniques

Domaines: Micro et nanotechnologies/Microélectronique

B. Sklenard, P. Batude, L. Pasini, C. Fenouillet-Beranger, B. Previtali, et al.. Low temperature junction formation by solid phase epitaxy on thin film devices: Atomistic modeling and experimental achievements. 2014 14th International Workshop on Junction Technology (IWJT), May 2014, Shanghai, China. pp.182-185, ⟨10.1109/IWJT.2014.6842024⟩. ⟨hal-02003838⟩