A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters

S. Cristoloveanu (1) , K.H. Lee (1) , S. Parihar (1) , H. El Dirani (1) , J. Lacord (2) , S. Martinie (2) , C. Le Royer (2) , Jean-Charles Barbé (2) , X. Mescot (1) , P. Fonteneau (3) , Ph. Galy (3) , F. Gamiz (4) , C. Navarro (4) , B. Cheng (5) , M. Duan (5) , F. Adamu-Lema (5) , A. Asenov (6) , Y. Taur (7) , Y. Xu (8) , Y-T. Kim (9) , J. Wan (10) , M. Bawedin (1)

1 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 ST-CROLLES - STMicroelectronics [Crolles]
4 UGR - Universidad de Granada = University of Granada
5 University of Glasgow
6 James Watt School of Engineering [Univ Glasgow]
7 ECE - UC San Diego - Department of Electrical and Computer Engineering [Univ California San Diego]
8 NJUPT - Nanjing University of Posts and Telecommunications [Nanjing]
9 The Korean Institute of Science and Technology
10 Fudan University [Shanghai]

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

Domaines: Micro et nanotechnologies/Microélectronique

S. Cristoloveanu, K.H. Lee, S. Parihar, H. El Dirani, J. Lacord, et al.. A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters. Solid-State Electronics, 2018, 143, pp.10-19. ⟨10.1016/j.sse.2017.11.012⟩. ⟨hal-02003277⟩