Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

R. Silveira Feitoza (1) , Manuel J. Barragan (1) , Daniel Dzahini (1) , Salvador Mir (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution Incremental Sigma-Delta converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.

Mots clés: Index Terms-Analog-to-Digital Conversion; Design-for-Test; Static Linearity Test; Reduced-code testing

Domaines: Micro et nanotechnologies/Microélectronique

R. Silveira Feitoza, Manuel J. Barragan, Daniel Dzahini, Salvador Mir. Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter. IEEE Transactions on Device and Materials Reliability, 2019, ⟨10.1109/TDMR.2019.2891298⟩. ⟨hal-01989117⟩