A path analysis based partitioning for time constrained embedded systems

Abstract : The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions that respect timing constraints and minimize an objective function such as the total area and/or the power consumption. Minimizing the hardware area conflicts with reducing execution time. Therefore, we introduce an heuristic for synthesizing heterogeneous systems that uses a global metric to guide the mapping of tasks according to the reusability of components and the time margin induced by timing constraints.
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Communication dans un congrès
IEEE. Int. Conference on Signal Processing Applications and Technology (ICSPAT, Mar 1998, Seattle, United States. IEEE, pp.85-89, 1998, 〈https://ieeexplore.ieee.org/document/666242〉
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https://hal.archives-ouvertes.fr/hal-01943417
Contributeur : Sophie Gaffé-Clément <>
Soumis le : lundi 3 décembre 2018 - 17:33:08
Dernière modification le : jeudi 6 décembre 2018 - 22:56:33

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  • HAL Id : hal-01943417, version 1

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Luc Bianco, Michel Auguin, Gogniat Guy, Alain Pegatoquet. A path analysis based partitioning for time constrained embedded systems. IEEE. Int. Conference on Signal Processing Applications and Technology (ICSPAT, Mar 1998, Seattle, United States. IEEE, pp.85-89, 1998, 〈https://ieeexplore.ieee.org/document/666242〉. 〈hal-01943417〉

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