Towards high density STT-MRAM at sub-20nm nodes

Abstract : STT-MRAM are attracting an increasing interest from microelectronics industry. They are about to enter in volume production with the first goal of replacing embedded Flash memory. To go towards high density STT-MRAM at sub-20nm nodes, two major issues have to be solved. One is the nanopatterning of the magnetic tunnel junctions at 1x feature size (F) and narrow pitch (pitch<2F). The other is to increase the thermal stability of the storage magnetization at sub-20nm nodes. This paper addresses these two issues and propose innovative approaches to solve these two difficulties.
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Submitted on : Thursday, December 6, 2018 - 4:37:12 PM
Last modification on : Thursday, April 4, 2019 - 9:44:02 AM
Long-term archiving on : Thursday, March 7, 2019 - 12:37:45 PM

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V. Nguyen, N. Perrissin, S. Lequeux, J. Chatterjee, L. Tille, et al.. Towards high density STT-MRAM at sub-20nm nodes. 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Apr 2018, Hsinchu, Taiwan. ⟨10.1109/VLSI-TSA.2018.8403867⟩. ⟨hal-01934201⟩

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