Incremental Learning on Chip

Ghouthi Boukli Hacene (1, 2, 3) , Vincent Gripon (1, 2, 3) , Nicolas Farrugia (1, 2, 3) , Matthieu Arzel (1, 2, 3) , Michel Jezequel (1, 2, 3)

1 Lab-STICC_IMTA_CACS_IAS
2 IMT Atlantique - ELEC - Département Electronique
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Learning on chip (LOC) is a challenging problem, which allows an embedded system to learn a model and use it to process and classify unknown data, adapting to new obser- vations or classes. Incremental learning of chip (ILOC) is more challenging. ILOC needs intensive computational power to train the model and adapt it when new data are observed, leading to a very difficult hardware implementation. We adress this issue by introducing a method based on the combination of a pre-trained Convolutional Neural Network (CNN) and majority vote, using Product Quantizing (PQ) as a bridge between them. We detail a hardware implementation of the proposed method validated on an FPGA target, with substantial processing acceleration with few hardware resources.

Mots clés: Field programmable gate arrays; Convolutional Neural Network; Transfer Learning; Incremental Learning; Learning on Chip

Domaines: Apprentissage [cs.LG]; Electronique; Traitement du signal et de l'image [eess.SP]

Ghouthi Boukli Hacene, Vincent Gripon, Nicolas Farrugia, Matthieu Arzel, Michel Jezequel. Incremental Learning on Chip. GlobalSIP 2017 : 5th IEEE Global Conference on Signal and Information Processing, Nov 2017, Montréal, Canada. ⟨10.1109/GlobalSIP.2017.8309068⟩. ⟨hal-01754847⟩